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1 ? fn6209.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2006. all rights reserved. all other trademarks mentioned are the property of their respective owners. isl59482 dual, 500mhz triple, multiplexing amplifiers the isl59482 contains two independent fixed gain of 2 triple 4:1 mux amplifiers th at feature high slew rate and excellent bandwidth for rgb video switching. each rgb 4:1 mux contains binary coded, channel select logic inputs (s0, s1), and separate logic inputs for high impedance output (hiz) and power-down (en ) modes. the hiz state presents a high impedance at the output so th at both rgb mux outputs can be wired together to form an 8: 1 rgb mux amplifier or, they can be used in r-r, g-g, and b-b pairs to form a 4:1 differential input/output mux. separate power-down mode controls (en 1, en 2, ) are included to turn off unneeded circuitry in power sensitive applications. with both en pins pulled high, the isl59482 enters a standby power mode- consuming just 34mw. features ? dual, triple 4:1 multiplexers for rgb ? 520mhz bandwidth into 500 load ? 1600 v/s slew rate ? externally configurable for various video mux circuits including: - 8:1 rgb mux - two separate 4:1 rgb mux - 4:1 differential rgb video mux ? internally fixed gain-of-2 ? high impedance outputs (hiz) ? power-down mode (en ) ? 5v operation ? supply current 16ma/ch maximum ? pb-free plus anneal available (rohs compliant) applications ? hdtv/dtv analog inputs ? video projectors, computer monitors ? set-top boxes ? security video ? broadcast video equipment ordering information table 1. channel select logic table isl59482 s1-1, 2 s0-1, 2 en1, 2 hiz1, 2 output1, 2 0 0 0 0 in0 (a, b, c) 0 1 0 0 in1 (a, b, c) 1 0 0 0 in2 (a, b, c) 1 1 0 0 in3 (a, b, c) x x 1 x power-down xx 0 1 high z part number (note) part marking tape & reel package (pb-free) pkg. dwg. # isl59482irz isl59482 irz - 48 ld exposed pad 7x7 qfn l48.7x7b ISL59482IRZ-T13 isl59482 irz 13? 48 ld exposed pad 7x7 qfn l48.7x7b note: intersil pb-free plus anneal products employ special pb-free material sets; mo lding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet december 22, 2006
2 fn6209.2 december 22, 2006 pinout isl59482 (48 ld qfn) to p vi e w functional diagram isl59482 36 35 34 33 32 31 30 48 47 46 45 44 13 14 15 16 17 1 2 3 4 5 6 7 outc1 outb1 v1- outa1 v1+ en1 hiz1 en2 gnd in1c2 in1b2 in1a2 gnd in0a2 s0-1 s1-1 in3c1 in3b1 in3a1 in2b2 in2c2 gnd in3a2 in3b2 8 9 29 28 18 43 19 in0b2 in0c2 in3c2 s1-2 in0c1 in0b1 gnd 42 41 40 39 38 in2c1 in2b1 in2a1 gnd inic1 37 in1b1 27 hiz2 26 25 v2+ 10 in0a1 11 12 gnd in1a1 20 21 22 s0-2 outc2 outb2 23 24 v2- outa2 in2a2 +2 +2 +2 +2 +2 +2 0 0 0 0 0 0 thermal pad pad must be tied to v- thermal pad internally connected to v- decode1 in0(a1, b1, c1) in1(a1, b1, c1) in2(a1, b1, c1) in3(a1, b1, c1) s0-1 s1-1 en0-1 en3-1 en2-1 hiz1 en1 amplifier1 bias en1-1 decode2 in0(a2, b2, c2) in1(a2, b2, c2) in2(a2, b2, c2) in3(a2, b2, c2) s0-2 s1-2 en0-2 en3-2 en2-2 hiz2 en2 amplifier2 bias en1-2 out(a1, b1, c1) out(a2, b2, c2) + - + - isl59482
3 fn6209.2 december 22, 2006 absolute maxi mum ratings (t a = +25c) supply voltage (v+ to v-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11v input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . v- -0.5v, v+ +0.5v supply turn-on slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1v/s digital and analog input current (note 1) . . . . . . . . . . . . . . . . 50ma output current (continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50ma esd rating human body model (per mil-st d-883 method 3 015.7). . . .2500v machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300v storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c ambient operating temperature . . . . . . . . . . . . . . . .-40c to +85c operating junction temperature . . . . . . . . . . . . . . .-40c to +125c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. if an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications v1+ = v2+ = +5v, v1- = v2- = -5v, gnd = 0v, t a = +25c, input video = 0.5v p-p and r l = 500 to gnd, c l = 5pf unless otherwise specified. parameter description conditions min typ max unit general + i s enabled enabled supply current no load, v in = 0v, en1, en2 low 77 88 96 ma - i s enabled enabled supply current no load, v in = 0v, en1, en2 low -90 -82 -70 ma +i s disabled disabled suppl y current no load, v in = 0v, en1, en2 high 4 6.8 7.6 ma -i s disabled disabled suppl y current no load, v in = 0v, en1, en2 high -80 -12 a v out positive and negative output swing v in = 2.5v, r l = 500 3.8 4.0 4.2 v i out output current r l = 10 to gnd 80 135 180 ma v os output offset voltage -60 - 25 20 mv ib input bias current v in = 0v -10 -2 +10 a r out hiz output resistance hiz = logic high 700 1000 1300 r out enabled output resistance hiz = logic low 0.1 r in input resistance v in = 1.75v 10 m a cl or a v voltage gain v in = 0.75v, r l = 500 1.94 1.99 2.04 v/v i hiz output current in three-state v out = 0v 15 a logic v ih input high voltage (logic inputs) 2 v v il input low voltage (logic inputs) 0.8 v i ih input high current (logic inputs) v h = 5v 200 260 320 a i il input low current (logic inputs) v l = 0v -10 -2 +10 a ac general psrr power supply rejection ratio dc, psrr v+ & v- combined v out = 0dbm 45 53 db xtalk channel to channel crosstalk f = 10mhz, chx-ch y-talk v in = 1vp-p; c l = 1.2pf 65 db off - iso off-state isolation f = 10mhz, ch-ch off isolation v in = 1vp-p; c l = 1.2pf 90 db dg differential gain error ntc-7, r l = 150, c l = 1.2pf 0.008 % dp differential phase error ntc-7, r l = 150, c l = 1.2pf 0.01 isl59482
4 fn6209.2 december 22, 2006 bw small signal -3db bandwidth v out = 0.2vp-p; r l = 500 , c l = 1.2pf 520 mhz v out = 0.2vp-p; r l = 150 , c l = 1.2pf 420 mhz large signal -3db bandwidth v out = 2vp-p; r l = 500 , c l = 1.2pf 250 mhz v out = 2vp-p; r l = 150 , c l = 1.2pf 230 mhz fbw 0.1db bandwidth v out = 2vp-p; r l = 500 , c l = 1.2pf 35 mhz v out = 2vp-p; r l = 150 , c l = 1.2pf 90 mhz sr slew rate 25% to 75%, r l = 150 , input enabled, c l = 1.5pf 1600 v/s transient response tr, tf large signal large signal rise, fall times, tr, tf, 10% - 90% v out = 2vp-p; r l = 500 , c l = 1.2pf 1.2 ns v out = 2vp-p; r l = 150 , c l = 1.2pf 1.2 ns tr, tf, small signal small signal rise, fall times, tr, tf, 10% - 90% v out = 0.2vp-p; r l = 500 , c l = 1.2pf 0.7 ns v out = 0.2vp-p; r l = 150 , c l = 1.2pf 0.8 ns ts 0.1% settling time to 0.1% v out = 2vp-p; r l = 500 , c l = 1.2pf 22 ns v out = 2vp-p; r l = 150 , c l = 1.2pf 24 ns ts 1% settling time to 1% v out = 2vp-p; r l = 500 , c l = 1.2pf 5 ns v out = 2vp-p; r l = 150 , c l = 1.2pf 7 ns switching characteristics v glitch channel-to-channel switching glitch v in = 0v, c l = 1.2pf 60 mv p-p en switching glitch v in = 0v, c l = 1.2pf 200 mv p-p hiz switching glitch v in = 0v, c l = 1.2pf 300 mv p-p t sw-l-h channel switching time low to high 1.2v logic threshold to 10% movement of analog output 22 ns t sw-h-l channel switching time high to low 1.2v logic threshold to 10% movement of analog output 25 ns tpd propagation delay 10% to 10% 0.9 ns electrical specifications v1+ = v2+ = +5v, v1- = v2- = -5v, gnd = 0v, t a = +25c, input video = 0.5v p-p and r l = 500 to gnd, c l = 5pf unless otherwise specified. (continued) parameter description conditions min typ max unit typical performance curves v s = 5v, r l = 500 to gnd, t a = +25c, unless otherwise specified. figure 1. small signal gain vs frequency vs c l into 500 load figure 2. small signal gain vs frequency vs c l into 150 load -10 -8 -6 -4 -2 0 2 4 6 8 10 1m 10m 100m 1g frequency (hz) normalized gain (db) c l = 2.2pf c l = 4.5pf c l = 2.7pf c l = 6.8pf c l includes 1.2pf board capacitance v out = 0.2vp-p c l = 1.2pf c l = 11.2pf c l = 3.4pf -10 -8 -6 -4 -2 0 2 4 6 8 10 1m 10m 100m 1g frequency (hz) normalized gain (db) c l = 3.9pf c l = 6.8pf c l = 11.2pf c l includes 1.2pf board capacitance v out = 0.2vp-p c l = 1.2pf c l = 16.2pf isl59482
5 fn6209.2 december 22, 2006 figure 3. gain vs frequency vs r l figure 4. 0.1db gain flatness figure 5. z out vs frequency - enabled figure 6. z out vs frequency - hiz figure 7. z in vs frequency figure 8. psrr vs frequency typical performance curves v s = 5v, r l = 500 to gnd, t a = +25c, unless otherwise specified. (continued) -5 -4 -3 -2 -1 0 1 2 1m 10m 100m 1g frequency (hz) normalized gain (db) r l = 1k r l = 250 r l = 150 r l = 500 -6 -7 -8 v out = 0.2vp-p c l = 1.2pf c l includes 1.2pf board capacitance -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.4 1m 10m 100m 1g frequency (hz) normalized gain (db) -0.5 -0.6 0.3 r l = 150 r l = 500 v out = 0.2vp-p c l = 1.2pf c l = 1.2pf 100 10 1 0.1 0.1m 1m 10m 100m 1g frequency (hz) output impedance ( ) v source = 2vp-p 10k 1000 100 10 0.1m 1m 10m 100m 1g frequency (hz) output impedance ( ) v source = 2vp-p v source = 2vp-p 1m 100k 10k 1k 100 10 1 input impedance ( ) frequency (hz) 0.3m 1m 10m 100m 1g v source = 2vp-p psrr (db) frequency (mhz) 0.3 1 10 100 1k 0 -20 -40 -60 10 -10 -30 -50 psrr (v+) psrr (v-) v source = 1vp-p isl59482
6 fn6209.2 december 22, 2006 figure 9. crosstalk and off isolation; figure 10. input noise vs frequency figure 11. differential gain and phase; v out =0.2vp-p f o =3.58mhz; r l =500 figure 12. differential gain and phase: v out =0.2vp-p f o =3.58mhz; r l =150 figure 13. small signal transient response; r l =500 figure 14. small signal transient response ; r l =150 typical performance curves v s = 5v, r l = 500 to gnd, t a = +25c, unless otherwise specified. (continued) frequency (hz) -10 -30 -50 (db) 0.3m 1m 10m 100m 1g -70 -90 off isolation input x to output x 0 -20 -40 -60 -80 -100 v in =1vp-p crosstalk input x to output y rl = 500 rl = 150 -110 -120 rl = 150 rl = 500 60 50 40 30 20 10 0 100 1k 10k 100k frequency (hz) voltage noise (n v/ hz ) normalized gain (db) 0.02 0 0 v out dc (volts) 0 1234 -4 -3 -2 -1 -0.002 0.002 -0.004 -0.006 -0.008 -0.01 -0.02 -0.04 -0.06 -0.08 -0.10 normalized phase ( o ) normalized gain (db) normalized phase ( o ) 0 0.01 -0.004 0.04 vout dc (volts) 0.02 0 0 1234 -4 -3 -2 -1 0.006 0.008 0.004 0.002 -0.02 -0.04 -0.06 -0.08 -0.10 -0.002 output voltage (v) 0.1 0 0.2 time (5ns/div) c l = 1.2pf v out = 0.2vp-p r l = 500 output voltage (v) 0.1 0 0.2 time (5ns/div) c l = 1.2pf v out = 0.2vp-p r l = 150 isl59482
7 fn6209.2 december 22, 2006 figure 15. large siglnal transient response; r l =500 figure 16. large signal transient response; r l =150 figure 17. pulse overshoot vs v out , c l ; r l =500 figure 18. pulse overshoot vs v out , c l ; r l =150 figure 19. channel to channel switching glitch v in =0v figure 20. c hannel to channel transient response v in =1v typical performance curves v s = 5v, r l = 500 to gnd, t a = +25c, unless otherwise specified. (continued) output voltage (v) 1.0 0 2.0 time (5ns/div) c l = 1.2pf v out = 2vp-p r l = 500 output voltage (v) 1.0 0 2.0 time (5ns/div) c l = 1.2pf v out = 2vp-p r l = 150 overshoot (%) 10 0 20 cl (pf) 30 40 50 2 4 6 8 10 v out = 2vp-p v out = 1.4vp-p v out = 1vp-p input rise, fall times v out = 0.2vp-p <175ps overshoot (%) 10 0 20 cl (pf) 30 40 50 2 4 6 8 10 v out = 2vp-p v out = 1.4vp-p v out = 1vp-p v out = 0.2vp-p input rise, fall times <175ps 1v/div 20mv/div 20ns/div 0 0 v in = 0v s0, s1 50 term. v out a, b, c 1v/div 1v/div 20ns/div 0 0 v in = 1v s0, s1 50 term. v out a, b, c isl59482
8 fn6209.2 december 22, 2006 figure 21. enable switching glitch v in = 0v figure 22. enable transient response v in = 1v figure 23. hiz switching glitch v in = 0v figure 24. hiz transient response v in = 1v figure 25. package power dissipation vs ambient temperature figure 26. package power dissipation vs ambient temperature typical performance curves v s = 5v, r l = 500 to gnd, t a = +25c, unless otherwise specified. (continued) 1v/div 0.5v/div 40ns/div 0 0 v in = 0v v out a, b, c enable 50 term. v in = 1v 1v/div 1v/div 40ns/div 0 0 v out a, b, c enable 50 term. 1v/div 100mv/div 20ns/div 0 0 v in = 0v s0, s1 50 term. v out a, b, c 1v/div 2v/div 20ns/div 0 0 v in = 1v s0, s1 50 term. v out a, b, c jedec jesd51-7 high effective thermal conductivity test board - qfn exposed diepad soldered to pcb per jesd51-5 6 5 4 3 2 1 0 0 25 50 75 100 150 ambient temperature (c) power dissipation (w) 4.34w ja =23c/w qfn48 125 85 jedec jesd51-3 low effective thermal conductivity test board - qfn exposed diepad soldered to pcb per jesd51-5 1.2 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 150 power dissipation (w) ja =115c/w qfn48 125 85 ambient temperature (c) 870mw isl59482
9 fn6209.2 december 22, 2006 pin description isl59482 (48 ld qfn) pin name equivalent circuit description 1 outc1 circuit 3 output of amplifier c1 2 outb1 circuit 3 output of amplifier b1 3, 23 v1-, v2- circuit 4a negative power supply #1 and #2 4 outa1 circuit 3 output of amplifier a1 5, 25 v1+, v2+ circuit 4a positive power supply #1 and #2 6en1 circuit 2 device enable (active low) w/internal pull-down resistor. a logi c high puts device into power-down mode leaving the logic circuitry active. this state is not recommended for logic control where more than one mux-amp share the same video output line. 26 en2 7 hiz1 circuit 2 output disable (active high) w/internal pull-down resistor. a logic high puts the output in a high impedance state. use this state when more than one mux-amp share the same video output line. 27 hiz2 8 in0c1 circuit 1 channel 0 input for amplifier c1 9 in0b1 circuit 1 channel 0 input for amplifier b1 10 in0a1 circuit 1 channel 0 input for amplifier a1 11 gnd circuit 4a ground pin for amplifier a1 12 in1a1 circuit 1 channel 1 input for amplifier a1 13 in2b2 circuit 1 channel 2 input for amplifier b2 14 in2c2 circuit 1 channel 2 input for amplifier c2 15 gnd circuit 4b ground pin for amplifier c2 16 in3a2 circuit 1 channel 3 input for amplifier a2 17 in3b2 circuit 1 channel 3 input for amplifier b2 18 in3c2 circuit 1 channel 3 input for amplifier c2 19, 47 s1-2, s1-1 circuit 2 channel select pin msb (binary logic c ode) for amplifiers a2, b2, c2 (s1-2) and a1, b1, c1 (s1-1) 20, 48 s0-2, s0-1 circuit 2 channel select pin lsb (binary logic c ode) for amplifiers a2, b2, c2 (s0-2) and a1, b1, c1 (s0-1) 21 outc2 circuit 2 output of amplifier c2 22 outb2 circuit 1 output of amplifier b2 24 outa2 circuit 1 output of amplifier a2 28 in0c2 circuit 1 channel 0 input for amplifier a2 29 in0b2 circuit 1 channel 0 input for amplifier b2 30 in0a2 circuit 1 channel 0 input for amplifier c2 31 gnd circuit 4b ground pin for amplifier a2 32 in1a2 circuit 1 channel 1 input for amplifier a2 33 in1b2 circuit 1 channel 1 input for amplifier b2 34 in1c2 circuit 1 channel 1 input for amplifier c2 35 gnd circuit 4b ground pin for amplifier b2 36 in2a2 circuit 1 channel 2 input for amplifier a2 37 in1b1 circuit 1 channel 1 input for amplifier b1 38 in1c1 circuit 1 channel 1 input for amplifier c1 39 gnd circuit 4a ground pin for amplifier b1 40 in2a1 circuit 1 channel 2 input for amplifier a1 41 in2b1 circuit 1 channel 2 input for amplifier b1 isl59482
10 fn6209.2 december 22, 2006 pin equivalent circuits figure 27a illustrates the optimum output load for testing ac performance. figure 27b illustrates the optimum output load when connecting to 50 input terminated equipment. 42 in2c1 circuit 1 channel 2 input for amplifier c1 43 gnd circuit 4a ground pin for amplifier c1 44 in3a1 circuit 1 channel 3 input for amplifier a1 45 in3b1 circuit 1 channel 3 input for amplifier b1 46 in3c1 circuit 1 channel 3 input for amplifier c1 pin description (continued) isl59482 (48 ld qfn) pin name equivalent circuit description in v+ v- logic pin v+ v- gnd 33k 21k + - 1.2v v+ v- out circuit 3 circuit 2 circuit 1 v1- ~1m substrate 1 v1- v1+ gndb1 capacitively coupled esd clamp gndc1 gnda1 v2- v2+ gndb2 capacitively coupled esd clamp gndc2 gnda2 circuit 4b circuit 4a thermal heat sink pad v2- ~1m substrate 2 ac test circuits figure 27a. test circuit with optimal output load figure 27b. test circuit for measuring with 50 or 75 input terminated equipment isl59482 c l 50 v in 500 r l 5pf or 75 isl59482 r s c l v in 475 test 5pf 50 or 75 50 or 75 50 or 75 equipment figure 27c. backloaded test circuit for video cable application. bandwidth and linearity for r l less than 500 will be degraded. figure 27. test circuits ac test circuits (continued) isl59482 r s c l v in 50 or 75 test 5pf 50 or 75 50 or 75 equipment isl59482
11 fn6209.2 december 22, 2006 application information general the isl59482 is ideal as the matrix element of high performance switchers and routers. key features include internal fixed gain of 2, high impedance buffered analog inputs and excellent ac performance at output loads down to 150 for video cable-driving. the current feedback output amplifiers are stable operating into capacitive loads. ground connections for the best isolation and cro sstalk rejection, all gnd pins must connect to the gnd plane. power-up considerations the esd protection circuits use internal diodes from all pins the v+ and v- supplies. in addition, a dv/dt- triggered clamp is connected between the v+ and v- pins, as shown in the equivalent circuits 1 through 4 section of the pin description table. the dv/dt triggered clamp imposes a maximum supply turn-on slew rate of 1v/s. damaging currents can flow for power supply rates-of-rise in excess of 1v/s, such as during hot plugging. under these conditions, additional methods should be employed to ensure the rate of rise is not exceeded. consideration must be given to the order in which power is applied to the v+ and v- pins, as well as analog and logic input pins. schottky diodes (motorola mbr0550t or equivalent) connected from v+ to ground and v- to ground (figure 28) will shunt damaging currents away from the internal v+ and v- esd diodes in the event that the v+ supply is applied to the device before the v- supply. one schottky can be used to protect both v+ power supply pins, and a second for the protection of both v- pins. if positive voltages are applied to the logic or analog video input pins before v+ is applied, current will flow through the internal esd diodes to the v+ pin. the presence of large decoupling capacitors and the loading effect of other circuits connected to v+, can result in damaging currents through the esd diodes and other active circuits within the device. therefore, adequate current lim iting on the digital and analog inputs is needed to prevent damage during the time the voltages on these inputs are more positive than v+. hiz state each internal 4:1 triple mux- amp has a three-state output control pin (hiz1 and hiz2). each has a an internal pull- down resistor to set the output to the enabled state with no connection to the hiz pin. the hiz state is established within approximately 20ns by placing a logic high (>2v) on the hiz pin. if the hiz state is selected, the output is a high impedance 1.4m with approximately 1.5pf in parallel with a 10 a bias current from the output. when more than one mux shares a common output, the high impedance state loading effect is minimized ov er the maximum output voltage swing and maintains its high z even in the presence of high slew rates. the supply current during this state is the same as the active state. en and power-down states the en pin is active low. an internal pull-down resistor ensures the device will be active with no connection to the en pin. the power-down state is established within approximately 80ns, if a logi c high (>2v) is placed on the en pin. in the power-down state, supply current is reduced significantly by shutting the th ree amplifiers off. the output presents a high impedance to th e output pin, however, there is a risk that the disabled am plifier output can be back-driven at signal voltage levels exceeding 2v p-p . under this condition, large incoming slew rates can cause fault currents of tens of ma. therefore, the parallel connection of multiple outputs is not recommended unless the application can tolerate the limited power-down output impedance. limiting the output current no output short circuit current limit exists on these parts. all applications need to limit the output current to less than 50ma. adequate thermal heat sinking of the parts is also required. v+ v+ v- v- v+ v- v+ v- logic control gnd in0 in1 s0 out external circuits schottky protection v+ v- power gnd signal logic v+ supply v- supply de-coupling caps figure 28. schottky protection circuit isl59482
12 fn6209.2 december 22, 2006 pc board layout the ac performance of this circuit depends greatly on the care taken in designing the pc board. the following are recommendations to achieve optimum high frequency performance from your pc board. ? the use of low inductance components such as chip resistors and chip capacitors is strongly recommended. ? minimize signal trace lengths. trace inductance and capacitance can easily limit circuit performance. avoid sharp corners, use rounded corners when possible. vias in the signal lines add inductance at high frequency and should be avoided. pcb traces greater than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. high frequency performance may be degraded for traces greater than one inch, unless strip line are used. ? match channel-channel analog i/o trace lengths and layout symmetry. this will minimize propagation delay mismatches. ? maximize use of ac de-coupled pcb layers. all signal i/o lines should be routed over c ontinuous ground planes (i.e. no split planes or pcb gaps under these lines). avoid vias in the signal i/o lines. ? use proper value and location of termination resistors. termination resistors should be as close to the device as possible. ? when testing use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. ? minimum of 2 power supply decoupling capacitors are recommended (1000pf, 0.01f) as close to the devices as possible. avoid vias between the cap and the device because vias add unwanted inductance. larger caps can be farther away. when vias are required in a layout, they should be routed as far away from the device as possible. ? the nic pins are placed on both sides of the input pins. these pins are not internally connected to the die. it is recommended these pins be tied to ground to minimize crosstalk. the qfn package requires additional pcb layout rules for the thermal pad the thermal pad is electrically connected to v- supply through the high resistance ic substrate. its primary function is to provide heat sinking for the ic. however, because of the connection to the v1- and v2- supply pins through the substrate, the therma l pad must be tied to the v- supply to prevent unwanted current flow to the thermal pad. do not tie this pin to gnd as this could result in large back biased currents flowing between gnd and the v- pins. maximum ac performance is achieved if the thermal pad is attached to a dedicated decoupled layer in a multi-layered pc board. in cases where a dedicated la yer is not possible, ac performance may be reduced at upper frequencies. the thermal pad requirements are proportional to power dissipation and ambient temperature. a dedicated layer eliminates the need for individual thermal pad area. when a dedicated layer is not possible, an isolated thermal pad on another layer should be used. pad area requirements should be evaluated on a case by case basis. mux application circuits each of the two 4:1 triple mux amplifiers have their own binary-coded, ttl compatible channel select logic inputs (s0-1, 2, and s1-1, 2). all three amplifiers are switched simultaneously from their respective inputs with s0-1 s1-1 controlling mux-amp1, and s0-2, s1-2 controlling mux-amp2. the hiz control inputs (hiz1, hiz2) and device enable control inputs (en1 and en2 ) control mux-amp1 and mux-amp2 in a similar fashion. the individual control for each 4:1 triple mux enables external connections to configure the device for different mux applications. 8:1 rgb video mux for a triple input rgb 8:1 mux (figure 4), the rgb amplifier outputs of mux-amp1 are parallel-connected to the rgb amplifier outputs of mux-amp2 to produce the single rgb video output. input channels ch0 to ch3 are assigned to mux-amp1, and channels ch4 through ch7 are assigned to mux-amp2. channels ch0 through ch3 are selected by setting hiz1 low, hiz2 high (enables mux-amp1 and three- states mux-amp2) and the appropriate channel select logic to s0-1, s1-1. reversing the logic inputs of hiz1, hiz2 switches from mux-amp1 to mux-amp2 enabling the selection of channels ch4 through ch7. the channel select inputs are parallel connected (s0-1 to s0-2) and (s1-1 to s1-2) to form two logic controls s0, s1. a single s2 control is split into complimentary logic inputs for hiz1 and hiz2 to produce a chip select function for the msb. the logic control truth table is shown in figure 29. 4:1 rgb differential video mux connecting the channel select pins in parallel (s0-1 to s0-2 and s1-1 to s1-2) converts the 8 individual rgb video inputs into 4 differential rgb input pairs. the amplifier rgb outputs are similarly paired resulting in a fully differential 4:1 rgb mux amp shown in figure 5. connecting hiz1 and hiz2 to +5v disables the 4:1 differential mux, and enables the connection of additional differen tial-connected mux amplifiers to the same outputs, thus allowing input expansion to 8:1 or more. isl59482
13 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6209.2 december 22, 2006 figure 29. application circuit for 8:1 rgb video mux s2 s1 s0 outa, b, c 0 0 0 ch0a, b, c 0 0 1 ch1a, b, c 0 1 0 ch2a, b, c 0 1 1 ch3a, b, c 1 0 0 ch4a, b, c 1 0 1 ch5a, b, c 1 1 0 ch6a, b, c 1 1 1 ch7a, b, c +2 +2 isl59482 1/3 mux-amp1 1/3 mux-amp2 outa1 in0a1 outa2 in1a2 in1a1 in2a1 in3a1 in0a2 in2a2 in3a2 s0-1 s1-1 hiz1 s0-2 s1-2 hiz2 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 s0 s1 s2 ch0a - ch7a channel select channels b & c not shown logic inputs channel select truth table 8:1 video mux control logic control logic outa figure 30. application circuit for 4:1 rgb differential video mux s1 s0 outa, b, c 0 0 ch0a, b, c 0 1 ch1a, b, c 1 0 ch2a, b, c 1 1 ch3a, b, c +2 +2 isl59482 1/3 mux-amp1 1/3 mux-amp2 outa outa1 in0a1 outa2 in1a2 in1a1 in2a1 in3a1 in0a2 in2a2 in3a2 s0-1 s1-1 hiz1 s0-2 s1-2 hiz2 ch0a - ch3a channel select channels b & c not shown logic inputs + - s0 s1 hiz ch0 ch1 ch2 ch3 + - + - + - + - channel select truth table 4:1 differential video mux control logic control logic isl59482
14 fn6209.2 december 22, 2006 isl59482 package outline drawing l48.7x7b 48 lead quad flat no-lead plastic package rev 0, 12/06 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 7.00 b a 7.00 (4x) 0.15 index area pin 1 top view pin #1 index area 44x 0.50 4x 5.5 48 37 3.70 1 36 25 48x 0 . 40 4 m 0.10 c ab 13 24 bottom view 12 5 0 . 2 ref 0 . 00 min. 0 . 05 max. detail "x" c 0 . 85 0 . 1 base plane see detail "x" c c 0.08 seating plane c 0.10 side view typical recommended land pattern 6 6 ( 6 . 80 typ ) ( 3.70 ) ( 48x 0 . 60 ) ( 44x 0 . 5 ) ( 48x 0 . 25 ) 0.25

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